AI Silicon Performance Modeling and Analysis Engineer
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
The AI Silicon Architecture and Performance Engineering team develops and maintains performance models enabling architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products.
These models provide early visibility into architectural tradeoffs, bottlenecks, and optimization opportunities.
We are seeking an experienced engineer to drive AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement.
The role focuses on performance modeling and analysis of AI SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement infrastructure using SystemC/TLM-based modeling methodologies.
Key responsibilities
- Develop, maintain, and enhance SystemC/TLM-based performance models representing critical AI silicon subsystems including SoC fabrics, memory controllers, and scale-up/scale-out interconnects.
- Define and execute comprehensive validation strategies, regression suites, and correlation workflows to ensure model correctness and architectural accuracy.
- Design and execute performance studies covering diverse AI workloads, traffic patterns, and system configurations to identify bottlenecks and evaluate scalability.
- Develop frameworks, automated workflows, and visualization tools using Python for large-scale performance data generation, analytics, and reporting.
- Partner closely with architecture, stimulus generation, silicon design, and product stakeholders to review proposals and influence design decisions.
- Drive improvements in modeling methodologies, simulation efficiency, automation, and team technical mentoring.
Qualifications
- Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or Electronics Engineering.
- Minimum 6+ years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, or performance engineering.
- Hands-on software development experience in C++ and working proficiency in Python for automation and performance analysis.
- Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
- Experience with SoC architecture, on-chip communication fabrics, NoC concepts, and high-speed interconnects.
- Experience with memory subsystem architecture, data movement, latency/bandwidth characterization, and bottleneck analysis.
- Experience performing architectural tradeoff analysis and performance debug studies for AI accelerators, SoCs, CPUs, GPUs, or hardware systems.
- Work authorization requirement: This position is not eligible for Intel immigration sponsorship.
Nice to have
- Deep understanding of AI accelerator architectures, modern AI infrastructure, and large language models.
- Experience modeling memory, communication, interconnect, or scalability-related subsystems.
- Familiarity with AI/ML workloads, distributed training, and inference environments.
- Experience building automated dashboards using Power BI, Tableau, Grafana, or Plotly.
- Experience evaluating large-scale distributed AI systems and accelerator clusters.
Benefits
- Competitive annual salary range of $141,910.00 to $232,190.00 USD.
- Total compensation package including competitive pay and stock bonuses.
- Comprehensive benefit programs including health, retirement, and vacation.
Job Type
Experienced Hire
- Location: US, California, Santa Clara
Work Model
Hybrid (splits time between working on-site at assigned Intel site and off-site)
- Shift: Shift 1 (United States of America)
About the company
Intel Corporation is a global industry leader in semiconductor technology, creating world-changing technology that enables global progress and enriches lives.
Intel is committed to driving innovation, fostering diversity, and maintaining ethical business practices across all operations.
Additional information
Intel is committed to Responsible Business Alliance compliance and ethical hiring practices. No fees are charged during the hiring process.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
Key details from the source
- Experience mentoring engineers and providing technical leadership in cross-functional environments.
Full listing
UpVagas condensed repetitive or legal boilerplate to make this page easier to read. The original hiring source contains the complete job description.
