Senior Analog and Mixed Signal Design Engineer
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of analog/mixed-signal and high-speed I/O IP that defines what Intel's leading-edge process technologies can deliver.
The High-Speed I/O team develops SerDes and die-to-die interface reference designs and test chips that co-optimize Intel process technology with next-generation wireline standards, including high-speed PAM4 electrical links, PCIe, UCIe, and HBM.
We are seeking a senior technical expert in high-speed SerDes circuit design and SerDes system architecture.
You will own SerDes link architecture on Intel's leading technology test chips, from link budget and equalization strategy down to transistor-level design of the critical analog front-end and clocking blocks.
Key responsibilities
- Define SerDes link architecture for next-generation interfaces (224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, UCIe) including channel analysis, link budget, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.
- Build and maintain system-level link models (statistical and time-domain, in MATLAB or Python; COM and IBIS-AMI based) and use them to derive block-level specifications for TX, RX, ADC, and clocking circuits.
- Lead transistor-level design of critical SerDes blocks: TX drivers (SST/CML) with FFE, RX AFE (CTLE, VGA, termination, T-coil and ESD co-design), DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, LC and ring PLLs, and clock distribution.
- Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; correlate measured BER, eye, jitter, and power against models, and lead root-cause analysis of silicon-to-model gaps.
- Translate SerDes requirements into process and PDK requirements (device fT/fmax and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability and aging) and drive design-technology co-optimization with process, PDK, and template-library teams.
- Provide technical leadership by mentoring engineers, leading design reviews, and representing Intel Foundry in technical engagements with IP partners and foundry customers.
Qualifications
- Bachelors Degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design experience -OR- Master's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline SerDes…
- Experience in Transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher.
- Experience in at least one of the following: SerDes link architecture (channel and link-budget analysis or equalization trade-off studies used to set block-level specifications), lab validation of high-speed links (BER, eye, or jitter measurement and correlation to simulation), or behavioral or statistical link modeling in MATLAB or Python.
Nice to have
- Experience with Silicon-proven designs at 56 Gb/s PAM4 or higher, in FinFET or GAA CMOS, with multiple tape-outs and block ownership.
- Experience across architecture, lab validation, and link modeling.
- Experience in ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design, 224 Gb/s-class link development (IEEE 802.3dj, OIF CEI-224G), and PCIe Gen6/Gen7 PHY or UCIe die-to-die PHY development.
- Design experience on 5nm-class or more advanced nodes, with design-technology co-optimization experience with process teams.
- Experience in package and channel co-design including package/PCB channel modeling, signal and power integrity, and crosstalk.
Benefits
- Competitive pay and stock bonuses
- Health, retirement, and vacation benefit programs
Job Type
Experienced Hire
- Shift: Shift 1 (United States of America)
Primary Location
US, Oregon, Hillsboro
Additional Locations
US, California, Santa Clara
Annual Salary Range
- $141,910.00-269,100.00 USD
Work Model
On-site presence required
About the company
Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal and high-speed I/O IP that defines what Intel's leading-edge process technologies can deliver.
Additional information
- Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices; no fees are charged during the hiring process.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
Key details from the source
- Experience with first-author publications at ISSCC, VLSI Symposium, CICC, or JSSC, or patents in SerDes circuits or architecture.
Full listing
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