Senior DFT Logic Design Engineer
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
Intel Foundry is a systems foundry transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era.
We provide an unparalleled blend of industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
The Aerospace, Defense, Government (ADG) group is seeking a Senior DFT Logic Design Engineer to provide technical support to Intel Foundry Services customers on our PDKs, DFT/DFM insertion, ATPG validation methodology, and flows.
Key responsibilities
- Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
- Create content, application notes, and deliver technical training and presentations.
- Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for block level and SOC level.
- Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.
- Apply strong analytical problem-solving skills with a customer-oriented, self-driven, and results-oriented mindset.
Qualifications
- US Citizenship required.
- Ability to obtain a US Government Security Clearance.
- Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
- 3+ years of experience with advanced CMOS processes (16nm and below).
- 3+ years of experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG, ...) at ASIC design block level and at full chip level, performing ATPG validation and DFT timing and DFT signoff at SOC level.
- 4+ years of experience in one or more scripting languages e.g. Python, Perl, Tcl, and/or shell scripting.
Nice to have
- Active US Government Security Clearance with a minimum of Secret level.
- Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
- Hands-on experience in one or more areas of Design Implementation and methodology such as ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, and Reliability.
- Experience using major EDA tools suites for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation, and ATPG validation for single die and multi-die design.
- Experience in building and developing quality DFT/DFX insertion flow and ATPG validation flow.
Benefits
- Competitive compensation including base salary and stock bonuses.
- Comprehensive health and retirement programs.
- Paid vacation time and professional development opportunities.
- Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications.
- Direct customer engagement and technical leadership in advanced semiconductor design.
Annual Salary Range
- $141,910.00 - $269,100.00 USD
- Location: US, Arizona, Phoenix; with additional locations in US, California, Santa Clara, and US, Oregon, Hillsboro
Work Model
Hybrid model allowing employees to split time between working on-site and off-site
Job Type
Experienced Hire
- Shift: Shift 1 (United States of America)
About the company
Intel Corporation is an industry leader focused on creating world-changing technology that enables global progress and enriches lives.
Inspired by our values, we are dedicated to driving digital transformation, advancing semiconductor manufacturing, and shaping the future of technology solutions for customers worldwide.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
Key details from the source
- Experience working with RTL and Hard IP designers on DFT/DFM implementation methodology.
- Experience working with physical designers on DFT/DFM physical implementation, validation, and DFT timing signoff.
- Semiconductor foundry experience and customer-facing background.
Full listing
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