Senior Silicon Architect – Cache Coherent Interconnects
NVIDIA
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
We are looking for a Senior Logic Design Engineer to join our CPU Cache Coherent Interconnects Design Team.
You will be responsible for the silicon architecture and construction of our CPU processors, focusing on dielet partitioning, packaging, die-stacking exploration, floorplanning, and die-to-die interface planning.
This role offers the opportunity to impact product lines ranging from consumer graphics to autonomous vehicles and artificial intelligence. You will collaborate with a global team pushing the frontiers of computing technology and defining future platforms.
Key responsibilities
- Own the silicon architecture and construction plan for next-generation CPU processors as a core CPU team member.
- Explore 2D multi-chip module, 2.5D interposer, and 3D hybrid-bonded dielet constructions, including IO and compute placement across dielets.
- Develop early floorplans and plan die-to-die and off-chip IO, including UCIe, DRAM, and PCIe.
- Collaborate with architecture, logic design, physical design, and packaging teams to achieve area, performance, power, and thermal goals.
Qualifications
- Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- Minimum of 8+ years of experience in processor or related high-performance semiconductor designs.
- Deep understanding of digital design, CPU system architecture, and ASIC floor-planning, including wire densities on-die and across 3D connected dies.
- Strong communication and interpersonal skills, with the ability to work in a dynamic, global team.
Nice to have
- Background in cache coherency or high-speed interconnects and industry-standard coherency, IO, or memory protocols.
- Knowledge of advanced packaging such as TSMC InFO, CoWoS, and Intel EMIB.
- Experience with through-silicon via configurations and backside power delivery.
- Familiarity with dielet, interposer, and substrate connectivity.
Benefits
- Base salary determined by location, experience, and other objective job-related factors.
- Equity eligibility.
- Comprehensive benefits package.
Job details
- Expected base salary range: 168,000 USD – 264,500 USD for Level 4, and 196,000 USD – 310,500 USD for Level 5.
- Application deadline: Accepted at least until November 3, 2026.
- Position type: Existing vacancy.
About the company
NVIDIA is a technology employer known for creating fast and power-efficient chips. We bring together brilliant and hardworking professionals globally to tackle challenging engineering problems and define the future of computing.
Additional information
- NVIDIA uses AI tools in its recruiting processes.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
