Silicon Packaging Design Architect
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About this opportunity
About the opportunity: Intel Corporation is seeking a Silicon Packaging Design Architect to join the Silicon Packaging Architecture team in Phoenix, Arizona.
In this senior engineering role, you will drive end-to-end package solutions meeting physical, electrical, and cost requirements while collaborating with cross-functional teams to improve packaging standards.
Your contributions will directly impact advanced 3D IC designs and ensure the seamless transition of cutting-edge silicon technologies to production.
This is an experienced hire position requiring an on-site presence in Phoenix, Arizona, operating on Shift 1. Candidates must be US citizens and possess the ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.
Key responsibilities
- Translate product requirements into detailed package architecture specifications.
- Drive technology tradeoff decisions to ensure silicon packages conform to electrical, mechanical, thermal, and reliability standards.
- Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions and overcome roadblocks.
- Oversee the end-to-end package development process, including design, procedures, and continuous improvements to quality standards.
- Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions.
- Implement co-design strategies between silicon and board design teams to optimize product performance and cost.
- Collaborate with EDA partners to advance package design tools and optimize design methods.
Qualifications
- US Citizenship required.
- Ability to obtain and maintain US Government TS/SCI Security Clearance with Polygraph.
- Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or a STEM related role with 6+ years of experience; or Master's degree with 4+ years of experience; or Ph.D. with 2+ years of experience.
- 2+ years of hands-on experience in semiconductor fabrication, chip assembly, or packaging.
- Experience in electromagnetic simulation tools such as Mentor, Cadence tools, SPICE, Ansys tools, or similar platforms.
- Experience with Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
- In-depth knowledge of assembly processes, test methodologies, and characterization techniques.
- Strong analytical, communication, and organizational skills, with the ability to manage multiple priorities in a dynamic environment.
Nice to have
- Active US Government TS/SCI Security Clearance with Polygraph.
- 10+ years of experience with profound knowledge in Package, PCB design, or IC digital design.
- Experience in troubleshooting and optimizing packaging designs for cost and quality.
- Experience in semiconductor fabrication and packaging processes.
- Experience collaborating with multidisciplinary teams across various levels of abstraction.
Benefits
- Competitive annual salary range of $164,470.00 to $311,890.00 USD.
- Stock bonuses.
- Comprehensive health programs.
- Retirement benefit programs.
- Paid vacation.
Job Type
Experienced Hire
- Shift: Shift 1 (United States of America)
- Location: US, Arizona, Phoenix
Work Model
On-site presence required
About the company: Intel Corporation is a dynamic and innovative ecosystem leader driving world-changing advancements in technology through cutting-edge silicon and advanced packaging solutions.
The company is committed to ethical hiring practices and Responsible Business Alliance compliance.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
Key details from the source
- Experience with technology trade-off decisions to ensure high-quality package outputs.
Full listing
UpVagas condensed repetitive or legal boilerplate to make this page easier to read. The original hiring source contains the complete job description.
