Sr. EDA Tools Engineer – PERC ESD
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
This position is within the Design Technology Platform (DTP) organization at Intel.
Specifically, the PERC ESD development team is looking for professionals to develop PERC ESD rule decks for the latest Intel technologies, enabling design teams to deliver leadership products faster on cutting-edge technologies.
As part of the DTP/Process Design Kit (PDK) group, you will join a highly motivated team solving challenging technical problems.
Your work will directly enable PDKs for Intel's most advanced process technologies and drive them toward industry-standard methods and ease of use for end customers.
Key responsibilities
- Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM) and reliability requirements.
- Create and maintain reliability ESD and LU design rule methodologies and specifications.
- Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors to define and implement new tool features and requirements.
- Build and execute test cases for rule debugging, validation, and signoff.
- Define QA requirements and drive related automation to improve robustness and efficiency of rule checks.
- Lead innovation initiatives to enhance existing ESD/LU verification automation, tools, and methodologies.
- Identify and analyze ESD/LU design problems, define root causes, and drive practical solutions across teams.
Qualifications
- Master's degree or PhD in Electrical Engineering or Computer Engineering.
- 2+ years of experience with ESD PERC rule decks/runset development and debugging, or equivalent reliability/DRC tools.
- 2+ years of experience in scripting (e.g., Python, Tcl, Perl, or similar) for QA and flow automation.
Nice to have
- 4+ years of experience with reliability/DRC tools.
- Industry experience in physical design verification including reliability, device physics, process technology, design rules, and extraction.
- Strong knowledge of ESD/LU PreSi models (HBM, CDM), I/O design, and related methodologies.
- Proven success working with cross-functional and cross-site teams.
- Experience driving cross-functional and industrywide initiatives or task forces.
Benefits
- Competitive pay and stock bonuses.
- Comprehensive health benefits.
- Retirement programs.
- Paid vacation time.
Job Type
Experienced Hire
- Shift: Shift 1 (United States of America)
Primary Location
US, Oregon, Hillsboro
Additional Locations
US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin
Annual Salary Range
- $149,600.00 - $284,580.00 USD
Work Model
On-site presence required
About the company
Intel is shaping the future of technology to help create a better future for the entire world.
Pushing forward fields like AI, analytics, and cloud-to-edge technology, Intel is at the heart of countless innovations that power major breakthroughs and improve our everyday quality of life.
Additional information
Intel is committed to ethical hiring practices and does not charge any fees during the hiring process.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
