TD Memory Quality and Reliability Engineer
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
The Technology Development (TD) Quality and Reliability organization at Intel enables the successful deployment of leading-edge process technologies through silicon-based quality, reliability, and technology readiness assessments.
The Memory Quality and Reliability team partners with Design, Device Engineering, Product Development Engineering, and Yield organizations to develop, characterize, and certify SRAM, Register File (RF), and Fuse arrays for advanced technology nodes.
We are seeking an experienced Memory Quality and Reliability Engineer to drive post-silicon memory characterization, certification, and technology readiness activities for advanced SRAM, Register File, and/or fuse arrays.
In this role, you will help improve certification methodologies, analyze large-scale silicon characterization data, develop Vccmin/Vmax predictive models, assess silicon-to-simulation correlation, and provide risk assessments that guide technology development and product deployment decisions.
Key responsibilities
- Plan and execute SRAM, RF, and/or Fuse technology certification supporting technology development and certification milestones.
- Define and maintain certification methodologies, criteria, test strategies, and readiness requirements for memory arrays.
- Drive memory array characterization across multiple operating conditions to evaluate Vmin, Vmax, aging behavior, variability, and design margins.
- Analyze silicon characterization data to identify performance gaps, failure signatures, systematic trends, and technology risks.
- Develop, validate, and maintain silicon-based Vccmin and Vmax predictive models used for technology certification, PDK releases, and product guidance.
- Perform silicon-to-simulation (Sil2Sim) correlation assessments and drive understanding of discrepancies between measured silicon behavior and design predictions.
- Collaborate with cross-functional teams to define root-cause hypotheses, resolution paths, and technology improvement recommendations.
- Generate certification reports, readiness assessments, and risk projections that support technology deployment decisions, presenting technical findings to leadership and stakeholders.
Qualifications
- Ph.D. in Electrical Engineering, Computer Engineering, Physics, or related discipline with 2+ years of semiconductor industry experience, OR M.S. in Electrical Engineering, Computer Engineering, Physics, Materials Science, or related discipline with 6+ years of semiconductor industry experience.
- 2+ years of hands-on experience with memory testing.
- 2+ years of experience performing quantitative analysis of large-scale memory or semiconductor datasets using statistical methods such as DOE, SPC, regression analysis, hypothesis testing, or multivariate analysis.
- 2+ years of hands-on experience using JMP and Python for data analysis, statistical modeling, process optimization, automation, or data visualization.
- Demonstrated ability to influence across organizational boundaries and drive resolution of complex technical challenges with a data-driven approach.
- Excellent written and verbal communication skills, with the ability to work independently in ambiguous, fast-paced technology development environments.
Nice to have
- Experience in memory design, characterization, validation, modeling, product development, quality, reliability, or technology development.
- Strong understanding of SRAM and/or Register File design fundamentals, silicon characterization techniques, and variability analysis.
- Experience developing silicon-based predictive models, statistical distributions, guardbands, and product risk projections.
- Knowledge of Vmin/Vmax characterization methodologies, memory margin assessment, array screening techniques, or design technology co-optimization.
- Experience with silicon-to-simulation correlation (Sil2Sim), SPICE modeling, or design validation.
Benefits
- Competitive total compensation package including competitive pay and stock bonuses.
- Comprehensive benefit programs including health, retirement, and vacation.
Job Type
Experienced Hire
- Shift: Shift 1 (United States of America)
Primary Location
US, California, Folsom
Additional Locations
US, California, Santa Clara, US, Oregon, Hillsboro
Annual Salary Range
- $155,520.00-255,200.00 USD
About the company
Intel Corporation is a global industry leader in semiconductor technology development, driving innovation through advanced silicon manufacturing, process technologies, and cutting-edge memory and computing solutions.
Additional information
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
We do not charge any fees during our hiring process.
Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
Key details from the source
- This role follows a hybrid work model allowing employees to split time between working on-site at an assigned Intel location and off-site.
- Programming experience in Python, JSL, SQL, or data analytics frameworks.
Full listing
UpVagas condensed repetitive or legal boilerplate to make this page easier to read. The original hiring source contains the complete job description.
