TD Memory Quality and Reliability PhD Intern
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
The Technology Development (TD) Quality and Reliability organization enables the successful deployment of next-generation semiconductor technologies through silicon-based quality, reliability, and technology readiness assessments.
The Memory Quality and Reliability team works closely with Design, Device Engineering, Product Development Engineering (PDE), and Yield organizations to develop, characterize, and certify SRAM, Register File (RF), and Fuse technologies for advanced process nodes.
As a TD Memory Quality and Reliability Intern, you will collaborate with experienced engineers to evaluate advanced memory technologies and help drive technology readiness for future Intel Foundry process nodes.
This role offers hands-on experience in memory characterization, silicon data analytics, statistical modeling, and semiconductor technology development.
Key responsibilities
- Analyze silicon characterization data from SRAM, Register File (RF), and Fuse memory test structures to identify performance trends, variability, and potential risks.
- Support memory characterization activities across voltage, temperature, and process conditions.
- Perform data analysis, visualization, and reporting using Python, JMP, or similar analytical tools.
- Develop and enhance statistical models for Vmin/Vmax prediction and technology readiness assessments.
- Support Silicon-to-Simulation (Sil2Sim) correlation studies and memory characterization methodologies.
- Generate technical reports and contribute to technology certification reviews.
- Collaborate with cross-functional teams including Design, Device Engineering, Process Integration, Product Development Engineering, and Yield Engineering.
- Assist with risk assessment activities and technology certification milestones.
- Present data-driven findings and recommendations to engineering teams and project stakeholders.
Qualifications
- Currently pursuing a Ph.D. in Electrical Engineering or a related field.
- Basic knowledge of semiconductor devices, microelectronics, or integrated circuit design.
- Programming or scripting experience using Python or similar languages.
- Experience analyzing technical, scientific, or research data through academic projects, research activities, or previous internships.
- Strong academic performance with a cumulative GPA of 3.0 or higher required.
Nice to have
- Coursework, research, or experience in SRAM or memory technologies, semiconductor device physics, VLSI design, statistics, machine learning, or data science, and semiconductor process technology.
- Experience with Python, Pandas, NumPy, JMP, or other statistical analysis tools.
- Experience with data visualization and statistical modeling techniques.
- Experience with large-scale data analysis and predictive modeling.
- Additional experience in memory architectures, silicon characterization, reliability assessment, or semiconductor test methodologies.
Benefits
- Competitive pay within an industry-leading total compensation package.
- Stock bonuses.
- Comprehensive health, retirement, and vacation benefit programs.
Job Type
Student / Intern
Primary Location
US, California, Folsom
Additional Locations
US, California, Santa Clara, US, Oregon, Hillsboro
Work Model
Hybrid work model (split time between working on-site and off-site)
Annual Salary Range
- $120,898.00 - $120,902.00 USD (standard internship rates based on degree, location, and job role)
- Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
Full listing
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