WPM Integration: Defect Engineer
Intel
Opportunity published from Workday · applications stay with the original hiring source.
About the opportunity
The Wafer Packaging Manufacturing organization is a global team driving Intel's advanced packaging technology and high-volume manufacturing (HVM).
WPM spans a broad portfolio including EMIB, Foveros, TSV reveal, C4 bumping, Die Prep, and Wafer Level Assembly to support strategic technologies across worldwide sites.
As a WPM Advanced Packaging Defect Reduction Engineer, you will protect yield and elevate defect performance across advanced semiconductor packaging processes.
You will partner with module engineering, QNR, manufacturing operations, and yield teams to deliver lasting solutions through a culture of trust and shared accountability.
Key responsibilities
- Own assigned advanced packaging layers, ensuring POR defect inspection, classification, and review operations are established with healthy recipes and NPI procedures.
- Drive ADC implementation for accurate defect classifications and maintain defect classification specs and Defect Menagerie for assigned layers.
- Partner with metro tool owners to set up and maintain SPC charts for every defect mode and layer, creating OCAPs for OOC events and defect tracers.
- Own process health, product quality, defect performance, yield trends, excursions, and baseline process changes for the WPM manufacturing line.
- Manage defect excursions through resolution, including containment, risk assessment, disposition, root cause, downstream impact, and quality events.
- Drive systematic defect reduction using process and metrology data, SORT data, DOEs, FRECLs, ATVs, and experiments with process modules.
- Co-lead cross-functional defect health reviews covering tracers, trends, OOCs, wafers-at-risk, excursions, and corrective actions.
- Extract, analyze, and correlate data to improve defects, yields, and VF matching using analysis, MBPS, and FA.
- Quantify chronic defect gaps to goal, document roadmaps, and ensure defect health dashboards are incorporated into factory business processes.
Qualifications
- Bachelor's degree in engineering or a related field with 3+ years of experience, OR Master's degree in engineering or a related field with 2+ years of experience, OR PhD in engineering or a related field with no prior professional experience.
- Experience in data extraction, synthesis, and analysis using SQL and Python.
- Experience in technology transfer and new product introduction (NPI) activities in semiconductor manufacturing.
- Expertise in failure analysis and data mining techniques to identify trends and drive actionable improvements.
- Proven ability to lead problem-solving initiatives and process improvement projects.
- Exceptional communication skills for collaborating across multidisciplinary teams.
- Passion for mentoring and fostering technical growth within teams.
Nice to have
- Strong understanding of semiconductor process flow, equipment, and process characterization techniques.
- Experience with design of experiments (DOE).
- Experience with statistical process control (SPC).
- Experience with process capability analysis.
Benefits
- Competitive base pay with an annual salary range of $103,730.00 to $146,440.00 USD.
- Stock bonuses.
- Comprehensive health programs.
- Retirement programs.
- Paid vacation and time off.
Job Type
Experienced Hire
- Shift: Shift 1 (United States of America)
Primary Location
US, New Mexico, Albuquerque
Additional Locations
US, Oregon, Hillsboro
Work Model
On-site presence required
Work Authorization
Not eligible for Intel immigration sponsorship
About the company
Intel is a global leader in semiconductor manufacturing and advanced packaging technology, committed to driving innovation and delivering groundbreaking solutions worldwide.
Additional information
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. No fees are charged during the hiring process.
Application: UpVagas lists this opportunity from the hiring company or its recruitment platform. The application is completed at the original source.
Key details from the source
- This role requires an on-site presence at the specified primary or additional locations and is not eligible for Intel immigration sponsorship.
Full listing
UpVagas condensed repetitive or legal boilerplate to make this page easier to read. The original hiring source contains the complete job description.
